1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device containing a large capacity memory such as a DRAM (Dynamic Random Access Memory) and a logic circuit such as a processor, which are integrated on a common semiconductor substrate, and in particular relates to a semiconductor integrated circuit device containing a synchronous memory operating in synchronization with a clock signal and a logic circuit in an integrated form. More particularly, the invention relates to a structure for externally testing the synchronous memory.
2. Description of the Background Art
Recently, a DRAM-embedded logic semiconductor integrated circuit device, in which a logic circuit such as a processor (which will be referred to merely as a "logic circuit" hereinafter) and a DRAM having a large storage capacity are integrated on a common chip (semiconductor substrate), has been developed. In this DRAM-embedded logic semiconductor integrated circuit device, it is possible to reduce a length of an interconnection line between the logic circuit and the DRAM, and a parasitic capacitance and a resistance of the interconnection line can be made small so that signals and data can be transmitted fast. Since the logic circuit and the DRAM are mutually connected only through internal interconnection lines, there is not restriction on the number of pin terminals. Therefore, a data bus width can be made wider to increase a bit width of data to be transferred, and therefore fast data transfer is allowed.
In the DRAM-embedded logic semiconductor integrated circuit device, only the logic circuit is coupled to the pin terminals through pads. Therefore, if functions of the embedded DRAM are to be tested, the test must be conducted through the logic circuit. In this case, however, the logic circuit performs the control for the test, and therefore a burden on the logic circuit increases. Also, the test must be performed in such a manner that an instruction for a function test of the DRAM is externally applied to the logic circuit, the logic circuit applies a control signal for the function test to the DRAM, and the result of the test is read out through the logic circuit. Thus, the function test of the DRAM is conducted through the logic circuit, and accurate tests of an operation timing margin of the DRAM and others cannot be performed. Also, the number of test patterns generated by the logic circuit is restricted due to a program capacity or the like so that the test cannot be conducted sufficiently, and it is impossible to determine the reliability of the DRAM with high accuracy. Accordingly, it becomes necessary to test externally and directly the DRAM through a dedicated test device.
FIG. 24 schematically shows a whole structure of a DRAM-embedded logic semiconductor integrated circuit. In FIG. 24, a DRAM-embedded logic semiconductor integrated circuit device (which will be referred to merely as a "semiconductor integrated circuit device" hereinafter) 900 includes a DRAM module 902, a logic circuit 904 which accesses data of DRAM module (macro) 902 and performs predetermined processing in accordance with an externally applied instruction or an embedded program, and a select circuit which selects either I/O nodes of logic circuit 904 or testing pads TPa, - - - , TPb, TPc, - - - and TPd for electrically connection to DRAM module 902 in accordance with a test mode instructing signal TE applied through a test pad 907. Logic circuit 904 is externally supplied with data or a signal through pads LPa, LPb, LPc, - - - , LPd, LPe, - - - and LPf. Generally, the semiconductor integrated circuit device 900 is provided with pads arranged along the periphery of the chip. FIG. 24 shows only some of the pads.
Select circuit 906 electrically connects testing pads TPa-TPb and TPc-TPd to DRAM module 902 when test mode instructing signal TE applied through pad 907 is active. DRAM module 902 includes a plurality of memory cells, a memory cell select circuit and a control circuit for the memory cell select circuit. In the structure shown in FIG. 24, DRAM module 902 can be externally and directly accessed by activating test mode instructing signal TE, for testing DRAM module 902 in accordance with a test program which has been conventionally used.
FIG. 25 shows a specific structure of the semiconductor integrated circuit device shown in FIG. 24. In FIG. 25, DRAM module 902 includes a data input node WD receiving write data of a 256-bit width, a control signal input node CD receiving a control signal, an address signal input node AD receiving an address signal of a 16-bit width, and a data output node RD supplying data of a 256-bit width.
For the test, there are provided a write data input pad WPD receiving write data of a 8-bit width, a control signal input pad CPD receiving a control signal, an address input pad APD receiving an address signal of 16 bits, a read data pad RPD receiving read data of an 8-bit width, and a data select address input pad SPD receiving an address signal for selecting data of 8 bits from the data of a 256-bit width read from DRAM module 902.
For write pad WPD, there is provided a distributing circuit 908 which extends the externally applied write data of 8 bits to test data of 256 bits. For read data pad RPD, there is provided a select circuit 909 for selecting data of 8 bits from data of 256 bits in accordance with an address signal for data selection applied from data select address pad SPD.
Select circuit 906 includes a switching circuit 906w selecting either the write data of 256 bits from logic circuit 904 or the write data of 256 bits from distributing circuit 908, a switching circuit 906c selecting the control signal from logic circuit 904 and the control signal from control signal input pad CPD, a switching circuit 906a for selecting one of the address signal of 16 bits from logic circuit 904 and the address signal of 16 bits from address input pad APD, and a switching circuit 906r for transmitting the data of 256 bits read from DRAM module 902 to one of logic circuit 904 and select circuit 909.
Connection paths of these switching circuits 906w, 906c, 906a and 906r are determined by test mode instructing signal TE. An operation of the semiconductor integrated circuit device shown in FIG. 25 will be described below with reference to FIG. 26.
Select circuit 906 connects pads CPD, APD and RPD to DRAM module 902 in accordance with activation of test mode instructing signal TE. Upon writing of data, an address signal A0 is applied to address input pad APD, and a write instructing signal (WRITE) instructing data writing is applied to control signal input pad CD. Write data WD0 is applied to write data input pad WPD. Distribution circuit 908 extends the write data to a data of 256 bits. The address signal, control signal and write data reach DRAM module 902 with a delay due to delays at internal interconnection in es extending from the pads, distribution circuit 908 and select circuit 906. Therefore, skews occur in the signals arriving at input nodes AD, CD and WD of DRAM module 902. When the signals arrive to DRAM module 902 and the signals on input node WD, CD and AD of DRAM module 902 are made definite, data writing is performed in DRAM module 902.
When data reading is to be performed, address signal A1 is applied to address input pad APD, as is done in the data writing, and a data read instructing signal (READ) is applied to control signal input pad CPD. Skews likewise occur on input nodes AD and CD of DRAM module 902 when address signal and control signal arrive at DRAM module 902 and are made definite. When the read instruction is applied, selection of the memory cell is performed in DRAM module 902 in accordance with address signal A1, and data RD1&lt;0:255&gt; of 256 bits appears on read data output node RD. When this read data appears, an address RDSA1 for data selection is applied to data select address input pad SPD. Due to an interconnection line delay between pad SPD and select circuit 909, a skew occurs in the data select address applied to node SD of select circuit 909 until it is defined. When data select address RDSA1 is definite on node SD of select circuit 909, data RD1&lt;0:7&gt; of 8 bits in 256 bits is selected and applied to read data output pad RPD. When the data reading is performed subsequently, read data from DRM module 902 changes so that a skew occurs on read data output node RD of DRAM module 902, and a skew likewise occurs on read data output pad RPD.
FIG. 26 shows that write data WD1 and WD2 are applied to write data input pads WPD even in the data read operation, only for clearly showing that a skew likewise occurs in the write data on write data input node WD of DRAM module 902. In the data read operation, it is not necessary to apply the write data to write data input pad WPD. Even if write data is applied, DRAM module 902 ignores the data applied to write data input node WD in data reading mode (by disabling the write data input buffer and write driver).
As shown in FIG. 26, the signals applied to the pads reach the corresponding nodes of DRAM module 902 through paths having different electrical characteristics, so that the definition timings shift due to interconnection line delays and the changed in bit numbers when the signals change, and skews occur.
DRAM module 902 takes in the address signal in accordance with the applied control signal, and allows the data access. An operation cycle for the test performed by externally and directly accessing DRAM module 902, which in turn takes in the address signal merely in synchronization with the control signal, is determined by a period from change in address signal applied to address input pad APD to the next change. DRAM module 902 selects a memory cell in accordance with the address signal which keeps a definite state for a period shorter than this operation cycle. Since the operation cycle of such DRAM module 902 is relatively long, the above skew occupies a short period in the operation cycle, and the influence exerted by this skew on the operation of the DRAM module can be substantially ignored.
Recently, such synchronous memories have been used that perform input/output of data and take in externally applied signals in synchronization with a clock signal different from the control signal. For example, input/output of data synchronized with a clock signal such as a system clock makes a data transfer speed equal to the speed of the clock signal. Since externally applied signals are taken in based on the clock signal, it is not necessary to give consideration to the shift (skew) in timing between external signals so that the internal circuits can start the operation at a faster timing, which allows fast access. A synchronous DRAM (SDRAM) is one of such kinds of synchronous memories. If this SDRAM is used in place of the DRAM module shown in FIG. 24 for data transfer between the logic circuit and the memory, the SDRAM module can operate in accordance with the clock signal so that it is possible to implement a DRAM-embedded logic semiconductor integrated circuit device capable of faster operation. In this case, a function test must be externally performed on the embedded SDRAM module (macro) for ensuring the reliability. For this, DRAM module 902 in the structure shown in FIG. 25 may be replaced with the SDRAM module.
FIG. 27 schematically shows a structure of a main portion of the SDRAM-module embedded logic semiconductor integrated circuit device. In FIG. 27, select circuit 906 which selects a signal transmission path in accordance with test mode instructing signal TE is arranged between an SDRAM module 910 and a logic circuit 912. Since SDRAM module 910 operates in synchronization with the clock signal, the clock signal is applied from logic circuit 912. During a test, SDRAM module 910 is externally supplied with a clock signal through a pad CKPD. Select circuit 906 includes a switching circuit 906ck for selecting one of the clock signal from logic circuit 912 and the clock signal from pad CKPD. Structures other than the above are the same as those shown in FIG. 25, and corresponding portions bear the same reference numerals.
SDRAM module 910 takes in signals applied to nodes WD, CD and AD in synchronization with clock signal CLK applied to its clock input node CKD, and outputs data from read data output node RD in synchronization with the clock signal. The operation of the semiconductor integrated circuit device shown in FIG. 27 will be described below with reference to a timing chart of FIG. 28.
In a test mode operation, test mode instructing signal TE is activated, and select circuit 906 isolates SDRAM module 910 from logic circuit 912 and sets SDRAM module 910 to a state allowing external access thereto through a pad. The clock signal applied to clock input pad CKPD is applied to clock input node CKD of SDRAM module 910 through select circuit 906. The clock signal applied to pad CKPD is merely applied to clock input node CKD of SDRAM module 910 with a delay.
The address signal is applied to address input pad APD in every clock cycle of the clock signal which in turn is externally applied to pad CKPD. The address signal applied to input pad APD has a plurality of bits, and a transition timing of each bit is different from the others so that a skew is present in the address signal reaching address input node AD of SDRAM module 910.
The control signal applied to control signal input pad CPD is applied to control signal input node CD of SDRAM module 910, and a skew likewise occurs when the state of the control signal changes. Since both the write operation instructing signal and read operation instructing signal change, consideration must be given on both the worst and best cases of the change (transition) timings of both the signals. Likewise, the write data applied to write data input pad WPD is 8-bit data, and is extended to 256 bits by distribution circuit 908, and is applied to SDRAM module 910 through select circuit 906, resulting in a skew. A skew likewise occurs in the address signal.
Address input pad APD is supplied with an address signal which is in the definite state at the rising of clock signal applied to clock input pad CKPD. SDRAM module 910 takes in the applied signal at the rising edge of clock signal applied to clock input node CKD. Therefore, it takes in address signal A1 applied in cycle #0 of the clock signal, which in turn is applied to clock input pad CKPD, in accordance with the data read instructing signal (READ) applied to control signal node CD, and the data reading is performed.
In SDRAM module 910, a memory cell is internally selected in accordance with this address signal A1. SDRAM module 910 has a structure similar to that of a conventional SDRAM, and a period which is called a column read latency (CAS latency) CL is required until the data is actually output after the data read instruction is applied. FIG. 28 shows the data read operation in the case where column read latency CL is 1. Therefore, data RD1&lt;0:255&gt; of the memory cell designated by this address signal A1 is made definite in cycle #1 of the clock signal applied to clock input pad CKPD. Data output node RD of SDRAM module 910 is coupled to select circuit 909 through select circuit 906r, and a skew occurs in the read data due to a load capacitance of this path. In cycle #1 of the clock signal applied to clock input pad CKPD, an address for data selection is applied to pad SPD, and select circuit 909 selects and outputs 8-bit data RD1&lt;0:7&gt; in accordance with a data select address RDSA1 applied to node SD.
In cycle #1 of the clock signal applied to clock input pad CKPD, the data read instruction is applied again, and next data is read in accordance with applied address signal A2. In cycle #2 of the clock signal applied to clock input pad CKPD, next data is likewise read in accordance with applied address signal A3. For the next read instruction, a data select address RDSA2 is applied, and next read data RD2&lt;0:7&gt; is read out. In this case, the selecting operation in select circuit 90 causes a skew in the read data applied to pad PRD.
FIG. 28 shows a state that write data WD1, WD2, WD3 and WD4 are also successively applied to write data input pad WPD in the data read operation. This is for clearly showing that a skew occurs in the write data transmitted to SDRAM module 910 when the write data changes. Even if the write data is applied during the data reading, SDRAM module 910 performs data reading in accordance with the read instruction, and does not perform the data writing so that no malfunction occurs. This is also true in such a case that an address RDSA for selecting the read data is applied during the data writing.
As shown in FIG. 28, the operation cycle of SDRAM module 910 is determined by the cycle of the clock signal applied to control signal input pad CKPD. This clock signal is a fast clock signal. Therefore, a proportion of the skew to the clock cycle in SDRAM module 910 is larger than that in asynchronous DRAM shown in FIGS. 24 and 25 even if the time widths of skews are equal to each other. SDRAM module 910 takes in externally applied data in synchronization with the rising edge of the clock signal applied to clock input node CKD, or outputs the data in synchronization with the same clock signal. If the skew is large, therefore, signals cannot be taken in accurately, and instructed operations cannot be performed accurately. If the skew is large, a period for which the signal applied to each input node of SDRAM module 910 is valid decreases. Therefore, an external test device must be operated under consideration of this skew caused when the operation mode instructing signal changes, and the clock cycle period effectively decreases, resulting in such a problem that fast external test of the SDRAM module is impossible.
In the SDRAM module shown in FIG. 28, the burst length (the number of data which is successively written/read per one data I/O node when data write/read instruction is applied) is one. However, even if the burst length is more than one, select circuit 909 shown in FIG. 27 performs the selecting operation during data reading. Therefore, a skew occurs in the read data, because the read data at node SPD changes at every clock cycle.
Column read latency CL can be changed in accordance with the clock cycle period of SDRAM module 910 because the time required for data reading is constant independently of the clock cycle.
FIG. 29 shows a data read operation with column read latency CL of 3. With column read latency CL of 3, SDRAM module 910 takes in the data read mode instruction together with the address signal in accordance with the clock signal applied to clock input node CLKD, and data RD1&lt;0:255&gt; of the addressed memory cell will be made definite after elapsing of 3 clock cycles. In cycle #3 of the clock signal applied to clock input node CKD of SDRAM module 910, the data is output.
When column read latency CL is changed, it is therefore necessary to apply externally the address signal for data selection to pad SPD in accordance with this changed column read latency, and it is necessary to change the timing of applying the address signal for data selection in accordance with the value of column read latency CL, resulting in disadvantageous increase in load on an external test device.
Therefore, a fast test cannot be performed if an SDRAM module operating in synchronization with a fast clock signal, is employed together with a structure for externally testing a clock-asynchronous DRAM module, which in turn takes in the address signal merely in accordance with signals /RAS and /CAS.